Open Source

 FPGA Hardware Acceleration over PCIe

This project intends to provide a system for hardware acceleration over PCIe on FPGA devices. The hardware part of the system is implemented on the Xilinx’s Virtex 7 VC707 FPGA development board. It is actually a hardware design that comprizes of hardware accelerators as well as several IP blocks that are required for the acceleration process. Part of the hardware design is a PCIe bridge which is used for the communication needs of the FPGA with the host system through the PCIe infrastructure. The hardware accelerator implements a Sobel filter algorithm for image processing. Several IP blocks such as the Sobel accelerator where developed with Xilinx’s Vivado HLS (High Level Synthesis).

The software components of the system include a userspace application and a kernel driver for the Linux host system and a standalone application for the Microblaze soft processor. The userspace application is developed as a use case where the host system offloads image processing tasks from a multi-threaded environment to hardware acceleration units over PCIe. The kernel driver establishes PCIe communication between a multi-threaded userspace application and the FPGA hardware design as well as distributing the hardware acceleration resources to the userspace threads. The Microblaze’s standalone application is mainly required to initialize the hardware design.

Source code can be downloaded from here.

CAN-bus Controller with AXI4-lite Interface

This project provides information and resources, in terms of hardware (synthesizable HDL code), software (C code) and documentation that enable the evaluation and testing of CAN-bus controllers operation and communication. Development boards equipped with FPGA and/or micro-controller and/or processor, which provides communicataion links between them, are suitable for porting this project. The provided sources have been tested over development boards equipped 32-bit ARM processors/micro-controllers, i.e., Zedboard (Xilinx Zynq-7000 + Cortex-A9) and SEcube (Lattice MachXO2 + Cortex-M4).

This work was partially funded by TAPPS Horizon2020 framework EU-funded project, ISCA-lab, colleagues and me, in order to fulfill project’s and lab’s goals. Demo videos related to TAPPS, with additional H/W and S/W extensions based on the requirements, can be found at ISCA-lab’s Youtube channel.

Source code can be downloaded from here.